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ASAHI KASEI
[AK6004A/08A]
I C bus 4K / 16Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.8V to 5.5V AK6004A 4096 bits, 512 x 8 organization AK6008A 16384 bits, 2048 x 8 organization I2CTM SERIAL INTERFACE LOW POWER CONSUMPTION - 0.8A Max. Standby HIGH RELIABILITY - Endurance : 100K cycles - Data Retention : 10 years 16 byte Page Write Mode Automatic write cycle time-out with auto-ERASE IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (SOP)
2
AK6004A / 08A
VCC GND WC
H.V.GENERATION TIMING & CONTROL
SDA
START STOP LOGIC CONTROL LOGIC XDEC WORD ADDRESS COUNTER
SCL S2 S1
SLAVE ADDRESS REGISTER +COMPARATOR
EEPROM
AK6004A = 4096bit AK6008A = 16384bit
YDEC
DATA REGISTER DOUT ACK
Block Diagram I2CTM is a registered trademark of Philips Corporation.
DAI01E-02 -12002/11
ASAHI KASEI
[AK6004A/08A]
General Description
The AK6004A/08A is a 4096/16384-bit serial CMOS EEPROM divided into 512/2048 registers of 8 bits each. The AK6004A/08A can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. The AK6004A/08A conforms to all specifications in the 2 wire protocol and is controlled by serial clock (SCL) and serial data (SDA) line. Some devices can be connected to the same bus. Each device connected to the bus is software addressable by a unique address, and can operate as either a transmitter or receiver. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table1). The master is the device which initiates a data transfers on the bus and generates the clock signals to permit that transfer. At that time, the device addressed is considered as the slave. TERM Transmitter Receiver Master Slave DESCRIPTION The device which sends the data to the bus The device which receives the data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by a master Table 1. Definitions Pin arrangement
AK6004A
NC S1 S2 GND 1 2 3 4 8 7 6 5 VCC WC SCL SDA
AK6008A
NC NC NC GND 1 2 3 4 8 7 6 5 VCC WC SCL SDA
Pin Name S1, S2 SCL SDA WC VCC GND NC Type of Products Model AK6004AF AK6008AF
DAI01E-02
Function Device Address Inputs Clock Input Data Input / Output Write Control Power Supply Ground Not Connected
Memory size 4K bits 16K bits
Temp. Range -40C to +85C -40C to +85C
-2-
VCC 1.8V to 5.5V 1.8V to 5.5V
Package 8pin Plastic SOP 8pin Plastic SOP
2002/11
ASAHI KASEI
[AK6004A/08A]
DATA TRANSFER All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK6004A/08A recognizes the START condition, the devices interfaced to the bus wait for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master.
[Data validity]
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
SCL
SDA DATA STABLE DATA CHANGE
Figure 1. Data transfer
[START and STOP condition]
A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. All commands are preceded by the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All communications are terminated by the STOP condition. After a read sequence, the STOP condition will place the EEPROM in a standby power mode.
SCL
SDA START CONDITION STOP CONDITION
Figure 2. Start and Stop Definition
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ASAHI KASEI
[AK6004A/08A]
[ACKNOWLEDGE]
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the next clock (ninth clock), the receiver will pull the SDA line to LOW to acknowledge that it received the eight bits of data. The AK6004A/08A will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the AK6004A/08A will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the AK6004A/08A slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition to return to the standby power mode.
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER
1
8
9
ACKNOWLEDGE
Figure 3. Acknowledge Response from Receiver
DAI01E-02 -4-
2002/11
ASAHI KASEI
[AK6004A/08A]
[SLAVE ADDRESS]
After the START condition, a SLAVE ADDRESS is sent. If the transmitted slave address matches an address of one of the device, the designated slave pulls the SDA line to LOW. AK6004A The most significant four bits of the slave address are fixed as "1010". The next two bits are S2, S1 device address bits. These two bits identify the specific device on the bus. They is set by the hard wired input pins (S1 pin and S2 pin). Therefore a total of four devices can be connected to the same bus. The next one bit is the most significant bit of the memory address. AK6008A The most significant four bits of the slave address are fixed as "1010". The next three bits are the most significant three bits of the memory address. The last bit of the slave address (R/W bit) defines whether a write or read condition is requested by the master. A "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed.
DEVICE ADDRESS 1 0 1 0 S2 S1 A8
MSB of memory address R/W
They is set by the hard-wired input pins (S1 pin and S2 pin).
Figure 4. Slave Address (AK6004A)
the most significant three bits of memory address 1 0 1 0 A10 A9 A8 R/W
Figure 5. Slave Address (AK6008A)
DAI01E-02 -5-
2002/11
ASAHI KASEI
[AK6004A/08A]
Pin Descriptions SCL (Serial Clock)
The SCL input is used to clock all data into and out of the device.
SDA (Serial Data)
The SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
S1, S2 (Device Address): AK6004A
The S1 and S2 are device address inputs that are used to set two bits of the slave address. AK6004A: A total of four devices can be connected to the same bus.
WC (Write Control)
AK6004A: If the WC is High level, WRITE operations will not be executed. If the WC is Low level, the AK6004A will be enabled to perform WRITE operation. AK6008A: If the WC is High level, WRITE operations onto the upper half of the memory (400 to 7FF(Hex)) will not be executed. If the WC is Low level, the AK6008A will be enabled to perform WRITE operation. As the WC is internally pulled down to GND, the AK6004A/08A will be enabled to perform WRITE operation if the WC is left floating. WC must not change from the start condition input to the stop condition input.
VCC (Power Supply) GND (Ground)
DAI01E-02 -6-
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ASAHI KASEI
[AK6004A/08A]
Functional Description WRITE Operations BYTE WRITE
A write operation requires a word address following the slave address word (R/W=0) and acknowledge. The word address is comprised of eight bits and provides access to any one of the 512/2048 words. Upon receipt of the word address the AK6004A/08A responds with an acknowledge, and awaits the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the AK6004A/08A begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the AK6004A/08A inputs are disable, and the device will not respond to any requests from the master.
S T A R T S T O P P
Bus Activity: Master
SLAVE ADDRESS
WORD ADDRESS
DATA
SDA LINE S
Bus Activity: AK6004A/08A
A C K
A7 - A0
A C K
A C K
: S2, S1, A8 (AK6004A) or A10, A9, A8 (AK6008A)
BYTE WRITE
PAGE WRITE
The AK6004A/08A is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation. But instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the AK6004A/08A will respond with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the AK6004A/08A begins the internal write cycle to the nonvolatile memory. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order five/seven bits of the word address remains constant. AK6004A: When the highest address is reached (X XXXX 1111), the address counter rolls over to address "X XXXX 0000" allowing the read cycle to be continued indefinitely. AK6008A: When the highest address is reached (XXX XXXX 1111), the address counter rolls over to address "XXX XXXX 0000" allowing the read cycle to be continued indefinitely. If the master should transmit more than sixteen words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. When the master transmit eighteen words prior to the stop condition, seventeenth word will be overwritten to first word, and eighteenth word will be overwritten to second word.
S T A R T S T O P P
Bus Activity: Master
SLAVE ADDRESS
WORD ADDRESS(n)
DATA(n)
DATA(n+1)
DATA(n+15)
SDA LINE S
Bus Activity: AK6004A/08A
A C K
A7 - A0
A C K
A C K
A C K
A C K
: S2, S1, A8 (AK6004A) or A10, A9, A8 (AK6008A)
PAGE WRITE
DAI01E-02 -72002/11
ASAHI KASEI
[AK6004A/08A]
ACKNOWLEDGE POLLING
Since the device will not acknowledge during the internal write cycle, this can be used to determine when the cycle is complete. This feature (ACK polling) can be used to maximize bus throughput. Once the stop condition is issued to indicate the end of the host's write operation the AK6004A/08A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the AK6004A/08A is still busy with the write operation no ACK will be returned. If the AK6004A/08A has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. When the write operation is executed after the ACK polling, the host can issue the byte address consecutively after the ACK is returned. When the read operation is executed after the ACK polling, the host should issue the stop condition once.
S T A R T S T O P P A C K S T A R T S
If the AK6004A/08A is still busy with the write operation, no ACK will be returned. If the AK6004A/08A has completed the write operation, an ACK will be returned.
Bus Activity: Master
SLAVE ADDRESS
SLAVE ADDRESS
SDA LINE S
Bus Activity: AK6004A/08A
A C K AK6004A/08A initiates
the internal write cycle.
WRITE command
ACKNOWLEDGE POLLING
ACKNOWLEDGE POLLING
DAI01E-02 -8-
2002/11
ASAHI KASEI
[AK6004A/08A]
READ Operations
There are three basic read operations: current address read, random read, and sequential read. Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. It is noted that the ninth clock cycle of the read operation is not a "don't care". To terminate a read operation, the master must hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
CURRENT ADDRESS READ
Internally the AK6004A/08A contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. Upon receipt of the slave address with R/W bit set to one, the AK6004A/08A issues an acknowledge and transmits the eight bit word. The master will not acknowledge the transfer but generate a stop condition, and therefore the AK6004A/08A discontinues transmission.
S T A R T S T O P P A C K
Bus Activity: Master
SLAVE ADDRESS
DATA
SDA LINE S
Bus Activity: AK6004A/08A
CURRENT ADDRESS READ
RANDOM READ
Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, slave address and then the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the AK6004A/08A and then by the eight bit word. The master will not acknowledge the transfer but generate the stop condition, and therefore the AK6004A/08A discontinues transmission.
S T A R T S T A R T S
Bus Activity: Master
SLAVE ADDRESS
WORD ADDRESS(n)
SLAVE ADDRESS
DATA(n)
S T O P P
SDA LINE S
Bus Activity: AK6004A/08A
A C K
A7 - A0
A C K
A C K
: S2, S1, A8 (AK6004A) or A10, A9, A8 (AK6008A)
RANDOM READ
DAI01E-02 -9-
2002/11
ASAHI KASEI
[AK6004A/08A]
SEQUENTIAL READ
Sequential read can be initiated as either a current read or random read. The first word is transmitted in the same manner as the other read modes. However the master responds with an acknowledge, indicating it requires additional data. The AK6004A/08A continues to output data for each acknowledge received. The data output is sequential, with the data from address n followed by the data from n+1. The master will not acknowledge the transfer but generate the stop condition, and therefore the AK6004A/08A discontinues transmission. AK6004A: When the highest address is reached ($1FF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. AK6008A: When the highest address is reached ($7FF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely.
SLAVE ADDRESS
Bus Activity: Master
A C K A C K
A C K
A C K
S T O P P
SDA LINE
Bus Activity: AK6004A/08A
DATA(n)
DATA(n+1)
DATA(n+2)
DATA(n+x)
SEQUENTIAL READ
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ASAHI KASEI
[AK6004A/08A]
Absolute Maximum Ratings
Parameter Power Supply All Input Voltages with Respect to Ground Ambient Storage Temperature Symbol VCC VIO Tst Min -0.6 -0.6 -65 Max +7.0 VCC+0.6 +150 Unit V V C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Power Supply Ambient Operating Temperature Symbol VCC Ta Min 1.8 -40 Max 5.5 +85 Unit V C
DAI01E-02 - 11 -
2002/11
ASAHI KASEI
[AK6004A/08A]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS (1.8VVCC5.5V, -40CTa85C, unless otherwise specified) Parameter Current Dissipation (WRITE) Symbol ICC1 ICC2 ICC3 Current Dissipation (READ) Current Dissipation (Standby) Input High Voltage Input Low Voltage Output Low Voltage ICC4 ICC5 ICC6 ICCS VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 Hysteresis of Schmitt trigger inputs (SCL, SDA) *2 Input Leakage Current *3 Output Leakage Current VHYS Condition AK6004A VCC=5.5V, fSCL=400KHz AK6008A AK6004A VCC=2.5V, fSCL=100KHz AK6008A AK6004A VCC=1.8V, fSCL=100KHz AK6008A VCC=5.5V, fSCL=400KHz VCC=2.5V, fSCL=100KHz VCC=1.8V, fSCL=100KHz VCC=5.5V *1 2.5VVCC5.5V 1.8VVCC<2.5V 2.5VVCC5.5V 1.8VVCC<2.5V 2.5VVCC5.5V IOL=4.5mA 1.8VVCC<2.5V IOL=3.0mA Min. Max. 3.0 3.5 2.5 3.0 1.5 2.0 500 200 100 0.8 VCC+0.5 VCC+0.5 0.3xVCC 0.2xVCC 0.4 0.4 0.05xVCC Unit mA mA mA mA mA mA A A A A V V V V V V V
0.7xVCC 0.8xVCC -0.3 -0.3
ILI ILO
VCC=5.5V, VIN=VCC/GND VCC=5.5V, VOUT=VCC/GND
1.0 1.0
A A
*1: VIN=VCC/GND, WC=GND *2: The parameter is periodically sampled and not 100% tested. *3: SCL, SDA, S1, S2
(2) CAPACITANCE (Ta=25C, f=1MHz, VCC=5.0V) Parameter Input / Output Capacitance (SDA) Input Capacitance (SCL) Symbol CI/O CIN Condition VI/O=0V VIN=0V Min. Max. 8.0 6.0 Unit pF pF
(Note) The parameter is periodically sampled and not 100% tested.
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ASAHI KASEI
[AK6004A/08A]
(3) A.C. ELECTRICAL CHARACTERISTICS 1: Standard mode (1.8VVCC5.5V, -40CTa85C, unless otherwise specified) Parameter SCK Clock Frequency Noise Suppression Time Constant at SCL, SDA *5 SCL Low to SDA Data Out Valid: SDA Time the Bus Must be Free before a New Transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data in Hold Time Data in Setup Time SDA and SCL Rise Time *5 SDA and SCL Fall Time *5 Stop Condition Setup Time Data Out Hold Time Write Cycle Time *4 *4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal program cycle. Since the device will not acknowledge during the internal program cycle, this can be used to determine when the cycle is complete. This feature (ACK polling) can be used to maximize bus throughput. *5: The parameter is periodically sampled and not 100% tested. tF tSU:STO tDH tWR 4.0 100 10 0.3 s s ns ms Symbol fSCL tI tAA1 tAA2 tAA3 tBUF Condition Min. Max. 100 100 3.5 3.5 4.5 Unit KHz ns s s s s
4.5VVCC5.5V 2.5VVCC<4.5V 1.8VVCC<2.5V
0.2 0.3 0.3 4.7
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR
4.0 4.7 4.0 4.7 0 250 1.0
s s s s s ns s
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ASAHI KASEI
[AK6004A/08A]
(4) A.C. ELECTRICAL CHARACTERISTICS 2: Fast mode (4.5VVCC5.5V, -40CTa85C, unless otherwise specified) Parameter SCK Clock Frequency Noise Suppression Time Constant at SCL, SDA *7 SCL Low to SDA Data Out Valid: SDA Time the Bus Must be Free before a New Transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data in Hold Time Data in Setup Time SDA and SCL Rise Time *7 SDA and SCL Fall Time *7 Stop Condition Setup Time Data Out Hold Time Write Cycle Time *6 *6: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal program cycle. Since the device will not acknowledge during the internal program cycle, this can be used to determine when the cycle is complete. This feature (ACK polling) can be used to maximize bus throughput. *7: The parameter is periodically sampled and not 100% tested. AC Conditions of Test Input Pulse Levels Input Rise and Fall Times Output Timing Level 0.1xVCC to 0.9xVCC 10ns 0.5xVCC
R= 466 (VCC=1.8V), 1133 (VCC=5.5V) C=100pF
Symbol fSCL tI tAA tBUF
Condition
Min.
Max. 400 50 0.9
Unit KHz ns s s
0.2 1.3
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR
0.6 1.3 0.6 0.6 0 100 0.3 0.3 0.6 50 10
s s s s s ns s s s ns ms
Equivalent AC Load Circuit
DAI01E-02 - 14 2002/11
ASAHI KASEI
[AK6004A/08A]
Synchronous Data Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO
SDA IN
tAA tDH tBUF
SDA OUT
BUS TIMING
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION
START CONDITION
WRITE CYCLE TIMING
DAI01E-02 - 15 -
2002/11
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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